Your argument is simple. A personality war!
Well, I can play the same game.
1. Missing the full Vega IP blocks doesn't materially change the result i.e. GTX 1070/R9-FuryX dropping bellow 60 fps and sustained on Scorpio.
Haven't you notice my comments for 2X R9-580 256 GB/s ~= Vega 10's 512 GB/s which lands RX-Vega into GP102 class range.
2. Missing the full Vega IP blocks doesn't materially change the result.
3. Scorpio *is* something else from PS4 Pro e.g. Scorpio has 40 active CU with faster 1172 Mhz clock speed over PS4 Pro's 36 active CU at 911 Mhz.
4. Part of Scorpio's optimizations are from Vega and it shows from it's superior results over RX-480/RX-580/R9-390X.
5. Wrong. Phil Spencer has identified existing AMD GPU problems and has pushed AMD to fix these hardware bottlenecks. The main goal for Scorpio is to run existing XBO 3D engines to 4K and to make it efficient with it's 6 TFLOPS.
6. You are questioning DF's credibility while removing Scorpio's significant bandwidth increase i.e "it's just RX-480" argument.
Plenty multi-layer near full screen semi-transparent effects are very taxing on any GPUs.
I doubled checked DF's claims with Battlefield 1, F1 2016 and FarCry Primal and I made sure it's RX-480/RX-580's results are memory bandwidth bottle-necked with R9-290's 4.8 TFLOPS being the reference point.
You even argued large very CPU memory bandwidth allocation for Scorpio while minimized PS4 Pro's CPU memory bandwidth allocation.
7. Stop being a hypocrite. Games like Witcher 3 and SF5 delivers similar results for PS4 and R7-265.
8. That's a shit post.
30 GB/s cache coherency is not a static memory bandwidth allocation. 30 GB/s cache coherency = the machine can track 30 GB/s worth of data changes before data corruption occurs. Beyond 30 GB/s data changes, the programmer must mark a memory location as cache incoherent which tell the cache coherency hardware to not track a particular memory location.
AMD APUs doesn't have fix CPU and GPU bandwidth allocation i.e. it's dynamic bandwidth allocation. A static memory bandwidth allocation is 1985 Amiga style CPU/IGP architecture and it's dead along time ago.
You failed at AMD's cache/DMA snoop function. DMA client device ask cache coherency tracker if memory page is being stored in CPU's cache and check if that cache data element has dirty/change state.
If cache coherency tracker answer is false(data element not in cache), DMA client device gets data from main memory.
If cache coherency tracker answer is true (data element stored in cache), DMA client device gets data from CPU' cache. At this point, Fusion link transfers data element from CPU's cache to DMA client device.
You failed at AMD's cache write back policy function i.e. only write dirty/change state data back to memory when evicted from CPU cache.
After dirty/change state data are write back to main memory, cache coherency tracker's table will be updated i.e. data element not stored in CPU cache.
You think AMD are noobs and has designed 1985 Amiga architecture. LOL.
9. Irreverent. Calling somebody a lem doesn't AMD PC APU facts.
10. DDR1? WTF?? PS4's 10 GB/s main memory for the CPU example is DDR2 range. Sony's CPU main memory allocation doesn't include memory bandwidth from fusion links e.g. 10 GB/s for main memory and 10 GB/s for fusion. Without fusion links, 20 GB/s is DDR3 range.
64bit DDR-400 = 3.2 GB/s
128bit DDR-400 = 6.4 GB/s
You don't know shit.
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