Sony NOT confident in the PS5???

That's why I am telling you that this information and more are disclosed in different avenues that are under NDA. You are not critically thinking if you think that Sony would be communicating key information about hardware to developers via public presentations like the one Cerny did.

For November 2020 release at this point, APU ASIC designs are locked.

XSX has the easy option to change four 1GB GDDR6 chips into 2GB version and enable its boost modes.

PS4's change from 0.5 GB chips into 1 GB chips already built into APU's design.

1. ROPS debates are useless without memory bandwidth debate.

2. Memory bandwidth debate is pointless without CU power debate. CU itself has TMU I/O.

There are 8 RB units for 64 ROPS.

10 RB units x 8 ROPS yields 80 ROPS. One extra RB unit for each Shader Engine cluster.

Techpowerup speculated that each RB unit has a GDDR6 chip.

320 bit / 256 bit = 1.25

1.25 x 64 ROPS = 80 ROPS.

1. It assumes AMD mastered NVIDIA style scaling with RDNA 2.

2. Note what I use RX 5600 XT's graphs since it has recent drivers.

@tormentos: You're a lost cause, I await for 5yrs down the road where you cut out my whole comment to a snippet that makes me look bad.

Enjoy those 9.2TF in 2025 when you can afford one LMFAO.

I don't care about power, never have, never will.

Its you cows who care, and you cows lose your shit when Sony loses ANYTHING to MS, just like you and tormy are, that's why I will make fun of you losers lol.

The xbox one has 16ROP and you could not stop damage controlling it.

Hell you still do..lol

Yes you do which is why you changed accounts into this alt.

And it shows on the first bold sentense there were you insist in using the power advantage of the xbox as some kind of ammo.

Worse in your case because you are inventing shit claiming the PS5 is 9.2TF when is not.

Not that it would change much if it was 9.2TF MS would still get beat up..lol

When 9.2 TFLOPS isn't enough, select Sony fannies continue to lose their minds.

My argument is not flawed and was backed by several PS4 games that had way a bigger gap than they should relative to the power advantage.

Never the less you downplayed it then just like you are downplaying it now thanks for proving me right.

So double the ROP only matter when the advatage is on xbox.

Meh you are not trying hard enough is to obvious.😁

It's not ROPS.

Early XBO middleware has manual 32 MB ESRAM programming requirements.

Midlife middleware has split 256bit DDR3 and 32MB eSRAM which presents a virtual 1920x1080p framebuffer to the programmer.

Midlife middleware fix wouldn't resolve XBO's CU bound issues.

HD 7970's 32 ROPS say Hi, hence your argument is flawed.

@ronvalencia said:

It's not ROPS.

Early XBO middleware has manual 32 MB ESRAM programming requirements.

Midlife middleware has split 256bit DDR3 and 32MB eSRAM which presents a virtual 1920x1080p framebuffer to the programmer.

Midlife middleware fix wouldn't resolve XBO's CU bound issues.

HD 7970's 32 ROPS say Hi, hence your argument is flawed.

Oh look you keep using the same pathetic image you use to post years ago as some kind of proof.

Again the pro has games thatb have way bigger gap than the 40% it had i am sure it was one of the reason.

NAVI 10's RBs (color and z-buffer ROPS) have high speed 4MB L2 cache links which are less bound by external bandwidth when compared to pre-Vega /pre-X1X ROPS.

Vega 64 ROPS gains 4MB L2 cache link. 4MB L2 cache is shared with TMUs.

X1X 32 ROPS gains 2MB render cache link. 2MB L2 cache is assigned to TMUs.

NVIDIA Maxwell architecture introduces ROPS with L2 cache link. GTX 980 Ti's 96 ROPS has ~3MB L2 cache with ~6 TFLOPS. 3MB L2 cache is shared with TMUs.

Most ROPS debates refer to color ROP count. Every color ROP unit has 4 z-buffer ROPS units e.g. 7970 has 32 color ROPS with 128 z-buffer ROPS

NAVI gains "DCC everywhere".

My argument changes when there are major design changes.

Note why PowerColor RX-5600 XT Red Devil OC's 192-bit bus penalty hit was just 8 percent from RX 5700.

PowerColor RX-5600 XT OC and RX 5700 have similar TFLOPS power with different memory bandwidth i.e. 336 GB/s vs 448 GB/s.

AMD is slowly following NVIDIA's improvement path.

For Sony's PS5, 448 GB/s shared memory bandwidth has RDNA's DCC everywhere and ROPS being connected to at least 4MB L2 cache and CPU with at least 8MB L3 cache (from PC Ryzen 4800HS series APU).

They were caught off guard and shocked by MS 12 Teraflops of power. PS5 was only 9.2. So then got desperate and try to overclock the Gpu as much as they could before it broke. That's what Cerny actually said.

@tormentos said:

@ronvalencia said:

It's not ROPS.

Early XBO middleware has manual 32 MB ESRAM programming requirements.

Midlife middleware has split 256bit DDR3 and 32MB eSRAM which presents a virtual 1920x1080p framebuffer to the programmer.

Midlife middleware fix wouldn't resolve XBO's CU bound issues.

HD 7970's 32 ROPS say Hi, hence your argument is flawed.

Oh look you keep using the same pathetic image you use to post years ago as some kind of proof.

Again the pro has games thatb have way bigger gap than the 40% it had i am sure it was one of the reason.

Killer Instinct Season 1 has 720p

Killer Instinct Season 2 has 900p

It's not ROPS when 7970 also has 32 ROPS.

From Mark Cerny

"When that worst case game arrives, it will run at a lower clock speed. But not too much lower, to reduce power by 10 per cent it only takes a couple of percent reduction in frequency, so I'd expect any downclocking to be pretty minor," he explains. "All things considered, the change to a variable frequency approach will show significant gains for PlayStation gamers."

1% less clock speed yields 10.173 TFLOPS, hence 19.4% difference from XSX.

2% less clock speed yields 10,070 TFLOPS, hence 20.6% difference from XSX.

...

There could be more clock speed reduction.

Mark Cerny warns CPU's AVX workload can cause clock speed throttle.