@endofaugust said:
I told you guys this would happen, it's not because people don't want an expensive 4K console, they want one that present enough value to be worth it. The Pro has not presented this value even at $400, it's very much a half-step to where it needs to be and is missing some things that were shortsighted on Sony's part and omitted. Microsoft was smart to wait a year, it garnered them a lot of incite and the ability to implement things based upon not only feedback of the Pro, but from the community in general, as a result they've brought a substantially more competent system into the fray and people want it.
With $499 price target, Sony could have asked AMD for PS4 NEO Option B. Sony doesn't need to wait for X1X's 384 bit GDDR5-6800 memory bus.
X1X's APU includes something that normal Polaris 10 doesn't have which is an update to RBE (Render Back Ends which includes ROPS) units.
X1X's non-L1 cache layout vs Vega 56/64's non-L1 cache layout
X1X has 2 MB L2 cache for TMU read/write + 2 MB rendering cache for ROPS read/write. Seems to be Polaris 36 percent memory compression boost. This is one of reasons why X1X's Forzatech's wet track with heavy alpha effects rivals GTX 1070 class GPUs. RBE's render cache and L2 cache are placed next to each other to lower latency.
Vega 56/64 has unified 4MB L2 cache for TMU and ROPS read/write. Seems to be Polaris 36 percent memory compression boost. Vega has HBC (high bandwidth cache below the L2 cache).
Against NVIDIA Paxwell GPUs
GTX 1070/1080 has unified ~2MB L2 cache for TMU and ROPS read/write. Pascal has 100 percent memory compression boost.
GTX 1080 Ti has unified ~3MB L2 cache for TMU and ROPS read/write. Pascal has 100 percent memory compression boost.
GTX 980 Ti has unified ~3MB L2 cache for TMU and ROPS read/write. Seems to be Maxwell V2 has 100 percent memory compression boost with Pascal era drivers.
Paxwell's ROPS access to large L2 cache is a known NVIDIA ROPS advantage.
AMD's Hawaii/Tonga/Fury/Polaris GPU's ROPS doesn't have direct access to L2 cache i.e. data must go through the memory controller bottleneck.
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