JEDEC Releases LPDDR4 Standard

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#1 Posted by NVIDIATI (8363 posts) -

LPDDR4 has been sampling since early 2014, and is expected to ship in devices in 2015. Qualcomm's Snapdragon 810 will be using LPDDR4 and is set to release in the first half of 2015.

JEDEC Releases LPDDR4 Standard for Low Power Memory Devices

ARLINGTON, Va., USA – August 25, 2014 – JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of JESD209-4 Low Power Double Data Rate 4 (LPDDR4). Designed to significantly boost memory speed and efficiency for mobile computing devices such as smartphones, tablets, and ultra-thin notebooks, LPDDR4 will eventually operate at an I/O rate of 4266 MT/s, twice that of LPDDR3. The new interface promises to have an enormous impact on the performance and capabilities of next-generation portable electronics. “LPDDR4 represents a dramatic performance increase,” said Mian Quddus, Chairman, JEDEC Board of Directors. “It is intended to meet the power, bandwidth, packaging, cost and compatibility requirements of the world’s most advanced mobile systems.” Developed by JEDEC’s JC-42.6 Subcommittee for Low Power Memories, the JESD209-4 LPDDR4 standard can be downloaded from the JEDEC website for free by clicking here.

Credit JEDEC

The full article can be found here.

Key specifications include:

  • Two-channel architecture
  • Internal Vref supplies for CA and DQ
  • Data Bus Inversion (DBI-DC)
  • ODT for CA and DQ
  • I/O throughput: 3200 MT/s, rising to 4266 MT/s
  • Signaling voltage: 367mV or 440mV
  • Operating voltage: 1.1V
  • Pre-fetch size: 32B per channel
  • Topology: Point to point, PoP, MCP
  • Max I/O capacitance: 1.3pF
  • Write leveling
  • 6-pin SDR CA bus CA training (12 pins per two channels)
  • As with previous low-power DRAM generations, LPDDR4 does not require a delay-locked loop (DLL) or phase-locked loop (PLL)
Credit JEDEC